Field programmable gate arrays (FPGAs) may be used in applications that require fast processing since FPGAs allow for all computations to occur on a single chip that has massive fine-grained parallelism. For example, FPGAs are used in the financial industry in high frequency trading where the rapid processing of the FPGA is desired. One technological problem with FPGAs is that there is a need to synchronize receiving side and transmitting side clock signals within the FPGA.
The prior art sought to address this problem by including a clock domain crossing circuit in the FPGA. However, these circuits inherently add a delay to the processing that takes place in the FPGA, which is not desirable since high frequency trading may include timestamps that are accurate to the microsecond such that even small delays may present a large problem.
Synchronous Ethernet systems were designed with the similar goal of synchronizing a transmitter to a receiver. However, since phase alignment in synchronous Ethernet is not necessary, synchronous Ethernet FPGA systems usually do not phase-align the receiver and transmitter sides of a link. The received clock is output from the transceiver to an external clock generation circuit to be used as its frequency reference. As a result, there is no measurement of the internal transmit clock at all by the Ethernet FPGA system.
While a synchronous Ethernet system with an internal PLL compares the transmit clock to the receive clock, its phase-frequency detector in the internal PLL is configured to measure accurately only the frequency but does not have to measure the phase of the two clocks accurately. In addition, synchronized protocols of the synchronous Ethernet system use simpler control loops that do not have to compensate for a lot of wander or jitter. Accordingly, the phase of the clocks is not treated as important as frequency by the synchronous Ethernet FPGA system. Based on these reasons, synchronous Ethernet FPGA systems do not provide a desirable solution to a technological problem of synchronizing receiving side and transmitting side clock signals within the FPGA.
Accordingly, a technical problem is presented in FPGAs in that phase synchronization between the receiver side clock and the transmitter side clock will introduce unwanted latency that results in delay of processing. Accordingly, it would be beneficial to provide an FPGA system that avoids these problems and provides sub-microsecond processing with throughput of at least 10 Gbps. In embodiments, the sub-microsecond processing throughput may be: 10-25 Gbps, 22-33 Gbps, 33-45 Gbps, 45-60 Gbps, 60-80 Gbps, 80-120 Gbps, to name a few.